The present invention relates to a liquid crystal display element and the method for manufacturing the same, and especially, to the structure of a liquid crystal display element providing improved display quality, reduced manufacturing cost and higher reliability when applied to a high definition large-sized display.
Along with the development of information technology, needs for laptop computers, portable data terminals, car navigation systems and the like have rapidly increased, accompanied by the active research and development of liquid crystal display devices. Liquid crystal display elements used in a liquid crystal display device forms a display pattern on the screen by selectively driving each pixel electrode arranged in matrix in the display device. When voltage is applied to the selected pixel electrode and an opposing electrode, the display medium mounted between these electrodes, such as the liquid crystal, is optically modulated, and recognized as a display pattern. One method for driving the pixel electrodes is the active matrix driving method, wherein independent pixel electrodes are aligned in the display, and each independent pixel electrode is connected to a switching element and driven by the same. Generally known as examples for the switching element used for selectively driving the pixel electrodes are the thin film transistor (hereinafter called TFT) and the MIM (metal-first insulation film-metal).
Resent trend of liquid crystal display panels is the large-sized high-definition panel, and active research is performed in this field. However, along with the increase in size of the panel or the glass substrate, it became increasingly difficult to provide a panel having homogeneous (even) display.
One cause of this problem is the superposition mismatch of the patterns, which results from performing plural numbers of photolithography when manufacturing the liquid crystal display element. When patterns are superposed during the repeated photolithography steps, there is generated within the substrate surface a region where the superposed areas Lxc2x7W of the gate electrode and the drain electrode differ ((L+xcex94x1)xc2x7W, (L+xcex94x2)xc2x7W, . . . ). When this occurs, the parasitic capacity proportional to that area ((L+xcex94x1)xc2x7W, (L+xcex94x2)xc2x7W, . . . ), that is, the parasitic capacity (Cgd) between the gate electrode and the drain electrode, is also dispersed within the substrate plane.
The degree of dispersion becomes conspicuous as the size of the glass substrate and the panel increases. This is mainly because (1) the accuracy of the exposure equipment used during the photolithography method is deteriorated as the size of the glass substrate and the panel increases; and (2) the influence of deflection of the glass panel starts to appear as the size of the glass substrate increases.
On the other hand, in the example of an active matrix liquid crystal display including TFT elements as its component, after a certain TFT element is selected and charged to a predetermined signal potential, and simultaneously when the gate is closed, the pixel potential is fluctuated for xcex94V. This is caused by the capacity coupling of the parasitic capacity (Cgd) between the gate electrode-drain electrode of the TFT element, the liquid crystal capacity (Clc) and the subsidiary capacity (Ccs). The size of xcex94V is computed by the following formula (1).
xcex94V=xcex94Vgxc2x7Cgd/(Cgd+Clc+Ccs)xe2x80x83xe2x80x83(1)
xcex94Vg: variation quantity of gate voltage
Cgd: parasitic capacity between gate electrode-drain electrode
Ccs: subsidiary capacity
When the value of Cgd in formula (1) is dispersed within the same panel plane, it means that xcex94V is dispersed, which leads to dispersion of the pixel potentials. As a result, problems such as display unevenness or flickering of the panel are caused.
Prior art examples 1 and 2 are used to explain the above-mentioned problems. First, the liquid crystal display element according to prior art example 1 comprises, as shown in FIG. 7(a) showing the explanatory plan view of a unit pixel and FIG. 7(b) showing the explanatory cross-sectional view taken at line A-Axe2x80x2 of FIG. 7(a), a liquid crystal layer (not shown), and a pair of transparent insulating substrates 21 facing each other with the liquid crystal layer positioned in between. Mounted on one of said pair of transparent insulating substrates 21 are a gate signal wire 22a; a source signal wire 29a formed orthogonal to the gate signal wire 22a; a laminated semiconductor layer formed near the crossing point of the gate signal wire 22a and the source signal wire 29a and including a gate electrode 22b, a gate insulation film 25, a semiconductor layer (a-Si layer) 26a, a semiconductor junction layer (n+-Si layer) 28, a channel protection film 27, a source electrode 29b, and a drain electrode 29c; and a pixel electrode 30 electrically connected to the laminated semiconductor layer. The channel protection film 27 has a side surface 273 positioned substantially perpendicular to the film surface, for example.
The method for manufacturing the prior art example 1 will now be explained with reference to FIGS. 8 and 9. Sputtering method is used to form a film made of Al, Mo, Ta or the like on a transparent insulating substrate 21. Then, through photolithography, a gate wire (not shown), a gate electrode 22b and a subsidiary capacity wire 23 are formed (refer to FIG. 8a).
Next, an anodic oxidation film 24 is formed through anodic oxidation. Subsequently, three layers each formed of a gate insulation film (SiNx) 25, an a-Si material 26, and a channel protection film 27 are continuously formed through CVD method. Then, a positive-type resist film is applied, the whole surface of which being exposed from the back surface of the transparent insulating substrate 21 using the gate electrode 22b as mask. The positive-type resist film pattern formed by developing the exposed film is used as a mask for etching the channel protection film 27 having an island-shaped pattern (refer to FIG. 8b).
Next, an n+-Si layer 28 is formed, to which is provided photolithography in order to form a contact layer that contacts the source electrode 29b and the drain electrode 29c. At this time, the lower layer formed of a-Si material 26 is patterned into an island-shape simultaneously when the n+-Si layer 28 is etched, and becomes the a-Si layer 26a (refer to FIG. 8c).
Next, a metal layer (source/drain metal) is formed using Mo, Ta and the like, which is then patterned into the desired shape through photolithography, forming a source signal wire 29a, a source electrode 29b and a drain electrode 29c (refer to FIG. 9d).
The TFT portion constituting the switching element of each individual pixel is formed according to the method explained above. Next, a transparent conductive film is formed using ITO and the like, which is then patterned to the desired shape through photolithography, forming a pixel electrode 30 (refer to FIG. 9e).
Next, a passivation film 31 formed of SiNx and the like is formed through CVD method, which is then patterned into the desired shape (refer to FIG. 9f).
According to the manufacturing method of prior art example 1, if the pattern of the source/drain electrode is displaced on the substrate surface, the overlapping area of the gate electrode 22b and the drain electrode 29c on the substrate or panel plane is changed. In other words, when in one area of the substrate, the overlapping area of the gate electrode 22b and the drain electrode 29c is Lxc2x7W1 as shown in FIG. 10(a) and (b), while in another area, the overlapping area is (L+xcex94x)xc2x7W2 as shown in FIG. 11(a) and (b) (W1≈W2≈W), than the parasitic capacity (Cgd) will increase in proportion to this increase in the overlapping area (xcex94xxc2x7W). As a result, the pixel potentials in the substrate or panel plane are dispersed, and the display becomes uneven.
In order to solve this problem, a liquid crystal display element and the method for manufacturing the same is proposed, that is capable of forming the source/drain electrodes in a self-matching manner and thereby reducing the inner-plane dispersion of the parasitic capacity (Cgd) between the gate electrode and the drain electrode caused by pattern mismatch.
The proposed prior art example 2 will now be explained with reference to FIGS. 12 through 15. The explanatory plan view of a unit pixel of the liquid crystal display element according to prior art example 2 is shown in FIG. 12. The A-Axe2x80x2 cross-sectional view of FIG. 12 showing each stage of the manufacturing steps are shown in FIGS. 13 and 14. The liquid crystal display element according to prior art example 2, similar to prior art example 1, comprises a liquid crystal layer (not shown), and a pair of transparent insulating substrates 41 facing each other with the liquid crystal layer positioned in between. On one of said pair of transparent insulating substrates 21 is formed a gate signal wire 42a, a source signal wire 49a formed orthogonal to the gate signal wire 42a, a laminated semiconductor layer mounted near the crossing point of the gate signal wire 42a and the source signal wire 49a and including a gate electrode 42b, a gate insulation film 45, a semiconductor layer (a-Si layer) 46a, a semiconductor junction layer (n+-Si layer) 48, a channel protection film 47, a source electrode 49b, a drain electrode 49c and so on, and a pixel electrode 50 electrically connected to the laminated semiconductor layer. The channel protection film 47 has aside surface 473 positioned substantially perpendicular to the film surface, for example.
The method for manufacturing the prior art example 2 will now be explained with reference to FIGS. 13 and 14. Sputtering method is used to form a film made of Al, Mo, Ta or the like on a transparent insulating substrate 41. Then, through photolithography, a gate wire (not shown), a gate electrode 42b and a subsidiary capacity wire 43 are formed (refer to FIG. 13a).
Next, an anodic oxidation film 44 is formed through anodic oxidation. Subsequently, three layers each formed of a gate insulation film (SiNx) 45, an a-Si material 46, and a channel protection film 47 are continuously formed through CVD method. Then, a positive-type resist film is applied, the whole surface of which being exposed from the back surface of the transparent insulating substrate using the gate electrode 22a as mask. The positive-type resist film pattern 52 formed by developing the exposed film is used as a mask for etching the channel protection film 47 having an island-shaped pattern (refer to FIG. 13b).
Next, while leaving on the positive resist 52 used for patterning the channel protection film 47, an n+-Si layer 48 and a metal film made of Mo, Ta and the like (source/drain metal) are sequentially formed on the substrate (refer to FIG. 13c), which is patterned to a desired shape through photolithography, thereby forming the source signal wire 49a, the source electrode 49b and the drain electrode 49c (refer to FIG. 14d). At this time, the a-Si material 46, the n+-Si layer 48, the source signal wire 49a, the source electrode 49b and the drain electrode 49c are patterned to the same shape. Further, by lifting off the positive resist used for patterning the channel protection film 47, there is formed a liquid crystal display element having a parasitic capacity (Cgd) between the drain electrode 49b and the gate electrode 42a that is not influenced by the mismatch of the patterns of the source electrode 49b and the drain electrode 49b (refer to FIGS. 15a and b).
The TFT constituting the switching element of each individual pixel is formed according to the method explained above. Next, a transparent conductive film is formed using ITO and the like, which is then patterned to the desired shape through photolithography, forming a pixel electrode 50 (refer to FIG. 14e).
Next, a passivation film 51 formed of SiNx and the like is formed through CVD method, which is then patterned to the desired shape (refer to FIG. 14f).
According to the method of prior art example 2, the inner-plane unevenness or the flickering of the display caused by mismatch of the superposed patterns is reduced, and the number of photolithography steps could be cut down. However, when the positive resist used for patterning the channel protection film 47 is not removed from the laminated structure before forming the n+-Si layer through CVD method on the structure, it caused serious problems to the TFT element such as (1) compound considered to be the reaction product of the film forming gas and the resist (which is an organic compound) being mixed into the chamber or the film as dust, and (2) bubbles appearing in the n+-Si film.
According to another prior art example, there is a proposal to form source electrodes on both sides of the drain electrode in order to prevent the fluctuation of parasitic capacity caused by mismatch of patterns (refer to Japanese Patent Laid-Open Publication No. 6-67199). According to yet another example, a proposal has been made to remove the resist film and to lift off the semiconductor junction layer or the source/drain metal film (refer to Japanese Patent Laid-Open Publication No. 5-55567). However, the prior art disclosures lack to consider patterning the source/drain electrodes in a self-matching manner by providing a channel protection film having an inverse tapered side surface.
The present invention aims at solving the problems of the prior art. The object of the present invention is to provide a liquid crystal display element having improved display quality, reduced manufacturing cost and higher reliability even when applied to a large high definition display, and the method for manufacturing the same.
The present invention provides a liquid crystal display element comprising: a pair of transparent insulating substrates facing each other with a liquid crystal layer in between; a thin-film transistor including a gate electrode formed on one of the pair of transparent insulating substrates, a gate insulation film formed on the gate electrode, a semiconductor layer formed on the gate insulation film, a channel protection film arranged on the semiconductor, a semiconductor junction layer formed on the channel protection film, a source electrode, and a drain electrode; and a pixel electrode; the thin-film transistor being arranged near each crossing point of a plurality of gate signal wires and source signal wires, the gate electrode being connected to the gate signal wire and one end of the source electrode being connected to the source signal wire in the vicinity of the crossing point, and one end of the drain electrode being connected to the pixel electrode; wherein the semiconductor junction layer, the other end of the drain electrode and the other end of the source electrode both being formed on the semiconductor junction layer are separated on the semiconductor layer by the channel protection film, the side surface of the channel protection film being formed as an inverse taper.
Moreover, the present invention provides a liquid crystal display element, wherein the semiconductor layer is an intrinsic semiconductor layer.
Even further, the present invention provides a liquid crystal display element, wherein the thickness of the channel protection film is 350 nm or more.
Moreover, the present invention provides a liquid crystal display element, wherein the ratio of the junction surface area of the channel protection film adjoining the passivation film being formed above the protection film and the junction surface area of the film adjoining the intrinsic semiconductor layer being formed below said film (area of the junction surface adjoining said passivation film/area of the junction surface adjoining said semiconductor layer) is 1.05 or more.
According to the present invention, the method for manufacturing a liquid crystal display element comprises the steps of: forming a gate signal wire and a gate electrode on a transparent insulating substrate; sequentially laminating on the upper surface of the gate signal wire and the gate electrode a gate insulation film, a semiconductor layer, and a channel protection film; applying a positive-type resist on the upper surface of the laminated transparent insulating substrate, the whole surface of the positive-type resist being exposed from the back surface of the transparent insulating substrate using the gate electrode as mask, and then etching the channel protection film using the developed and formed positive-type resist film pattern as mask so that the side surface of the channel protection film is formed as an inverse taper; etching the semiconductor layer using the channel protection film having an inverse tapered side surface as mask; and sequentially laminating on the transparent insulating substrate a semiconductor junction layer and a material for forming source signal wire, source electrode, and drain electrode, then forming the source signal wire, the source electrode and the drain electrode using as mask a resist film formed by applying, exposing and developing a resist material.
According to the above-explained invention, the source electrode and the drain electrode could be formed in a self-matching manner, realizing a structure where the parasitic capacity (Cgd) between the drain electrode and the gate electrode is not influenced by the mismatch of the pattern of the source/drain electrodes. In other words, according to the invention, problems such as inner-plane unevenness or the flickering of the display are reduced. According further to the present invention, the patterning of both the channel protection film and the semiconductor layer is performed by a single photolithography step, which enables to cut down the number of photolithography steps compared to the prior art method.